The present invention relates to a thin film transistor and a method of manufacturing the same. More particularly, the present invention relates to a thin film transistor which is suitable for incorporation into a static random access memory (SRAM).
In general, thin film transistors may be used instead of load resistors in SRAMs having densities exceeding 1 megabit. Thin film transistors are also widely used as switching elements for switching image data signals in pixel regions of a liquid crystal display device.
Ideally, in either application, the off current of the thin film transistor should be low, while on current should be high in order to reduce power consumption and improve memory characteristics. That is, the thin film transistor should have a high on/off current ratios.
Much research has focused on achieving a thin film transistor with improved on/off current ratios.
A method for manufacturing a thin film transistor in an attempt to achieve an improved on/off current ratio is shown in FIGS. 1a-1e. In particular, these figures illustrate processing steps for manufacturing a conventional bottom gate thin film transistor on a semiconductor substrate.
As shown in FIG. 1a, a first insulating film 2 is formed on a semiconductor substrate 1. After depositing a polysilicon layer 3 on first insulating film 2, polysilicon layer 3 is patterned by conventional photolithography and etching techniques according to a gate mask, thereby forming a gate electrode 3a.
As shown in FIG. 1b, through a chemical vapor deposition (CVD) method, a gate insulating film 4 and a polysilicon body layer 5 are successively deposited on the entire exposed surface of gate electrode 3a and first insulating film 2. Then, during a 24 hour heat treatment growth step, the wafer is subjected to a temperature of approximately 600.degree. C. As a result, the grain size of polysilicon layer 5 is enlarged.
As shown in FIG. 1c, a photoresist film is next coated on body polysilicon layer 5 and patterned by conventional exposure and development processes to form a photoresist pattern PR.sub.1, which masks a channel region. At this time, with photoresist pattern PR.sub.1 serving as an ion-implantation mask, impurity ions are implanted into the exposed body of polysilicon layer 5, thereby forming source region 6a and drain region 6b (FIG. 1d).
Accordingly, where the impurity ions are not implanted in polysilicon body layer 5, a channel region A is formed, while another region between gate electrode 3a and drain region 6b serves as off-set region B.
As shown in FIG. 1e, after removing photoresist pattern PR.sub.1, a second insulating film 7 is formed on the entire surface of channel region A, off-set region B, source region 6a and drain region 6b. Second insulating film 7 is then patterned to form contact holes to source region 6a and drain region 6b, respectively. Then, the contact holes are filled with a conductor to thereby form a source electrode 8 and a drain electrode 9 as wiring electrodes.
The operation principle of such conventional thin film transistor is as follows.
To begin with, if the transistor shown in FIG. 1e is a P-type MOS thin film transistor, channel region A has n conductivity, and source region 6a and drain region 6b have p conductivity. Accordingly, if a negative voltage is applied to gate electrode 3a relative to source region 6a, holes accumulate in channel region A, thereby forming a channel. If a negative voltage is applied to drain region 6b relative to source region 6a, a current flows between source region 6a and drain region 6b, due to the potential difference between the source and drain. However, if no voltage is applied to gate electrode 3a, a channel is not formed, and current is disrupted.
As shown in FIGS. 1a to 1e, channel region A and offset region B are both defined using photoresist pattern PR.sub.1. However, if photoresist pattern PR.sub.1 is misaligned, high off-current can result, thereby reducing reliability of the above-described thin-film transistor.
Further, while the conductivity of off-set region B is adjusted in order to decrease the off-current, the conductivity of region B is not affected by the potential on gate electrode 3a. Thus, the series resistance is increased, causing drain current drivability to deteriorate.